diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -86,6 +86,8 @@
 /* Analog Register Part: reg08 */
 #define PLL_POST_DIV_ENABLE_MASK		BIT(5)
 #define PLL_POST_DIV_ENABLE			BIT(5)
+#define DATA_LANE_VOD_RANGE_SET_MASK		GENMASK(3, 0)
+#define DATA_LANE_VOD_RANGE_SET(x)		UPDATE(x, 3, 0)
 #define SAMPLE_CLOCK_DIRECTION_MASK		BIT(4)
 #define SAMPLE_CLOCK_DIRECTION_REVERSE		BIT(4)
 #define SAMPLE_CLOCK_DIRECTION_FORWARD		0
@@ -389,10 +391,11 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
 			REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
 	if (inno->pdata->max_rate == MAX_2_5GHZ) {
 		phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
-				PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
+				PLL_POST_DIV_ENABLE_MASK | DATA_LANE_VOD_RANGE_SET_MASK,
+				PLL_POST_DIV_ENABLE | DATA_LANE_VOD_RANGE_SET(VOD_BIG_RANGE));
 		phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
 				CLOCK_LANE_VOD_RANGE_SET_MASK,
-				CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
+				CLOCK_LANE_VOD_RANGE_SET(VOD_BIG_RANGE));
 	}
 	/* Enable PLL and LDO */
 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,