From dac564896d22f6c3f5c791425732d219d98b7cdf Mon Sep 17 00:00:00 2001
From: avishad verma <avishad.verma@infineon.com>
Date: Tue, 22 Aug 2023 03:57:57 -0500
Subject: [PATCH 260/296] brcmfmac: FW Header Changes to TRXv5 for
 H1-CP/Combo-A1

Fw header is changes to Trxv5 for H1-CP.
Changes are done to support TrxV5 Header.
Ram start  offsets are updated for H1-A1.

Fixes: SWWLAN-147338

Signed-off-by: avishad verma <avishad.verma@infineon.com>
---
 .../broadcom/brcm80211/brcmfmac/chip.c        | 24 ++++++++++++++-----
 .../broadcom/brcm80211/brcmfmac/sdio.c        |  5 +++-
 .../broadcom/brcm80211/brcmfmac/trxhdr.h      | 12 ++++++++++
 3 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
index 5f7b5c0188a2..9cbacaf0ea82 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
@@ -240,7 +240,7 @@ struct sbsocramregs {
 #define CYW55572_RAM_BASE	(0x370000 + \
 				 CYW55572_TCAM_SIZE + CYW55572_TRXHDR_SIZE)
 
-/* 55500, Dedicated sapce for TCAM_PATCH and TRX HDR area at RAMSTART */
+/* 55500-A0, Dedicated sapce for TCAM_PATCH and TRX HDR area at RAMSTART */
 #define CYW55500_RAM_START	(0x3a0000)
 #define CYW55500_TCAM_SIZE	(0x800)
 #define CYW55500_TRXHDR_SIZE	(0x2b4)
@@ -248,6 +248,13 @@ struct sbsocramregs {
 #define CYW55500_RAM_BASE	(CYW55500_RAM_START + CYW55500_TCAM_SIZE + \
 				 CYW55500_TRXHDR_SIZE)
 
+/* 55500-A1, Dedicated sapce for TCAM_PATCH and TRX HDR area at RAMSTART */
+#define CYW55500_A1_TCAM_SIZE	(0x1000)
+#define CYW55500_A1_TRXHDR_SIZE	(0x20)
+
+#define CYW55500_A1_RAM_BASE	(CYW55500_RAM_START + CYW55500_A1_TCAM_SIZE + \
+				 CYW55500_A1_TRXHDR_SIZE)
+
 #define BRCMF_BLHS_POLL_INTERVAL			10	/* msec */
 #define BRCMF_BLHS_D2H_READY_TIMEOUT			100	/* msec */
 #define BRCMF_BLHS_D2H_TRXHDR_PARSE_DONE_TIMEOUT	50	/* msec */
@@ -825,10 +832,10 @@ static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
 		return 0x352000;
 	case BRCM_CC_4387_CHIP_ID:
 		return 0x740000;
+	case CY_CC_55500_CHIP_ID:
+		return ((ci->pub.chiprev == 0) ? CYW55500_RAM_BASE : CYW55500_A1_RAM_BASE);
 	case CY_CC_55572_CHIP_ID:
 		return CYW55572_RAM_BASE;
-	case CY_CC_55500_CHIP_ID:
-		return CYW55500_RAM_BASE;
 	default:
 		brcmf_err("unknown chip: %s\n", ci->pub.name);
 		break;
@@ -848,9 +855,14 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
 		mem_core = container_of(mem, struct brcmf_core_priv, pub);
 		ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
 
-		if (ci->pub.chip == CY_CC_55500_CHIP_ID)
-			ci->pub.ramsize -= (CYW55500_TCAM_SIZE +
-					    CYW55500_TRXHDR_SIZE);
+		if (ci->pub.chip == CY_CC_55500_CHIP_ID) {
+			if (ci->pub.chiprev == 0)
+				ci->pub.ramsize -= (CYW55500_TCAM_SIZE +
+						CYW55500_TRXHDR_SIZE);
+			else
+				ci->pub.ramsize -= (CYW55500_A1_TCAM_SIZE +
+						CYW55500_A1_TRXHDR_SIZE);
+		}
 
 		if (ci->pub.chip == CY_CC_55572_CHIP_ID)
 			ci->pub.ramsize -= (CYW55572_TCAM_SIZE +
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
index c83f4286a2d9..64f3b21462b7 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
@@ -3991,7 +3991,10 @@ static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
 			err = -EIO;
 	} else {
 		if (trx->magic == cpu_to_le32(TRX_MAGIC)) {
-			address -= sizeof(struct trx_header_le);
+			if ((trx->flag_version >> 16) == TRX_VERSION5)
+				address -= sizeof(struct trxv5_header_le);
+			else
+				address -= sizeof(struct trx_header_le);
 			fw_size = le32_to_cpu(trx->len);
 		}
 
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/trxhdr.h b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/trxhdr.h
index 0411c7c7ffb9..14c327ef856e 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/trxhdr.h
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/trxhdr.h
@@ -35,4 +35,16 @@ struct trx_header_le {
 	__le32 offsets[TRX_MAX_OFFSET];	/* Offsets of partitions */
 };
 
+#define TRX_VERSION5	5			/* Version 5 */
+
+struct trxv5_header_le {
+	__le32 magic;		/* "HDR0" */
+	__le32 len;			/* Length of file including header */
+	__le32 crc32;		/* 32-bit CRC from flag_version to end of file */
+	__le32 flag_version;	/* 0:15 flags, 16:31 version */
+	__le32 root_cert_start_offset;	/* Start Offset IDX for Root Certificate */
+	__le32 content_cert_start_offset;	/* Start Offset IDX for Content Certificate */
+	__le32 fw_entry;	/* Firmware Entry Point for CM mode */
+	__le32 reserved;
+};
 #endif /* BRCMFMAC_TRXHDR_H */
-- 
2.25.1

